In recent years, an electronic device has come to be integrated with high density, and a semiconductor chip with multiple terminals is packaged in accordance with an improvement of the function and thinning of an electronic circuit. Accordingly, a package of the semiconductor chip used in the electronic circuit is miniaturized and provided with multiple pins. In conformity with the aforementioned tendency, the semiconductor chip is assembled into a printed circuit board by means of a package of an area array type, such as a ball grid array package (BGA), a chip scale package (CSP) or a bare chip package (a flip chip package, FC).
FIG.1 shows a typical example of the structure of the aforementioned packages of the semiconductor chips. In the package shown in FIG. 1, a chip-mounting substrate 103 on which a semiconductor chip 100 has been mounted by means of wire-bonding is assembled into a printed circuit board 104 by CSP; where the chip-mounting substrate 103 is composed of an insulating substrate 101 formed of ceramics, polyimide, etc. and conductor wirings 102.
In the package having the aforementioned structure, a clearance formed between the chip-mounting substrate 103 and the printed circuit board 104 is filled with underfill material 105 in order to absorb a stress caused by a difference in the thermal expansion coefficient between the chip-mounting substrate 103 and the printed circuit board 104 and impacts caused by fallings to secure the reliability of soldered jointed portions.
However, if alien substances mix with underfill material 105 or the impacts exert on under fill material 105 for a long period of time, an adhesive strength of underfill material 105 is lowered, and underfill material 105 may exfoliate form the surface of the chip-mounting substrate 103 or of the printed circuit board 104.
If underfill material 105 exfoliates from the chip-mounting substrate 103 or the printed circuit board 104, the stress concentrates on joined portions of the solder balls 106, cracks occur on pads 107, 108, which are respectively formed on surfaces of the chip-mounting substrate 103 and the printed circuit board 104, and the joined portions become disconnected. As mentioned in the above, the reliability of the semiconductor device is lowered because of lowering of the adhesive strength of the underfill material 105.
In Japanese Patent Applications, Laid-Open, No. 63-94646, an electronic device in which unevennesses are respectively provided for a predetermined part of a chip-mounting substrate and sealing resin for sealing a semiconductor chip is disclosed as a means for increasing an adhesive strength between the chip-mounting substrate and the basic substrate. That is to say, in the aforementioned semiconductor device, concave portions and convex portions are alternately formed on the chip-mounting substrate and on sealing resin for covering the semiconductor chip, and the chip-mounting substrate on which the semiconductor chip is mounted is buried in a cavity formed in the basic substrate. Accordingly, the aforementioned technology cannot be applied to a package of an area array type.
Although a semiconductor device in which a bonding wire is prevented from being disconnected by providing unevenness for a pad is disclosed in Japanese Patent No. 2973988, underfill material is not prevented from being exfoliated according to this technology.
In a semiconductor device in which a semiconductor chip mounted on a lead frame is assembled into a printed circuit board, since there is a difference in a thermal expansion coefficient between the lead frame and a pad of the printed circuit board, the lead frame may exfoliate from the printed circuit board at a contact surface therebetween because of an impact caused by a thermal shock.